Sort By

Semi-custom

UTB 36 - Part-2: ASIC Physical Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (Netlist-to-GDSII) cover

UTB 36 - Part-2: ASIC Physical Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (Netlist-to-GDSII)

Navaneetha Krishnan

UTB36 - Part-1: ASIC Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (RTL-to-Netlist) cover

UTB36 - Part-1: ASIC Design and Verification of I2C(Inter-Integrated Circuit) Protocol using Cadence EDA Tools (RTL-to-Netlist)

Ashwini H, Pooja C

UTB35 - Part-2: ASIC Physical Design and Verification of FIFO using Cadence EDA Tools (Netlist-to-GDSII) cover

UTB35 - Part-2: ASIC Physical Design and Verification of FIFO using Cadence EDA Tools (Netlist-to-GDSII)

Navaneetha Krishnan, Pooja C

UTB35 - Part-1: ASIC Design and Verification of FIFO (First In-First Out) using Cadence EDA Tools (RTL-to-Netlist) cover

UTB35 - Part-1: ASIC Design and Verification of FIFO (First In-First Out) using Cadence EDA Tools (RTL-to-Netlist)

Ashwini H, Pooja C

UTB34(b) - Part-2: ASIC Physical Design and Verification (Netlist-to-GDSII) of a Mod-N(Mod-10) Counter cover

UTB34(b) - Part-2: ASIC Physical Design and Verification (Netlist-to-GDSII) of a Mod-N(Mod-10) Counter

Dr Mamidi Nagaraju, Ashwini H

UTB33(b) - Part-2: ASIC Physical Design and Implemetation of SPI Protocol (Netlist-to-GDSII) cover

UTB33(b) - Part-2: ASIC Physical Design and Implemetation of SPI Protocol (Netlist-to-GDSII)

Dr Mamidi Nagaraju

UTB33(a) - Part 1: ASIC Design and Verification of SPI Communication Protocol using Cadence EDA Tools (RTL-to-Netlist) cover

UTB33(a) - Part 1: ASIC Design and Verification of SPI Communication Protocol using Cadence EDA Tools (RTL-to-Netlist)

Dr Mamidi Nagaraju

UTB31 (b) - Part-2: Physical Design and Verification of PWM Generator (Netlist-to-GDSII) cover

UTB31 (b) - Part-2: Physical Design and Verification of PWM Generator (Netlist-to-GDSII)

Dr Mamidi Nagaraju

UTB31 (a) - Part-1: ASIC Design and Verification of PWM Generator (RTL-to-Netlist) cover

UTB31 (a) - Part-1: ASIC Design and Verification of PWM Generator (RTL-to-Netlist)

Dr Mamidi Nagaraju, Ashwini H

UTB29 Part-2: Back-end ASIC Implementation of Chip-Level MAC Unit (Netlist-to-GDSII) cover

UTB29 Part-2: Back-end ASIC Implementation of Chip-Level MAC Unit (Netlist-to-GDSII)

Dr Mamidi Nagaraju, Ashwini H

UTB29 Part:1 -ASIC Design and Verification of MAC Unit (RTL-to-Netlist) cover

UTB29 Part:1 -ASIC Design and Verification of MAC Unit (RTL-to-Netlist)

Dr Mamidi Nagaraju, Ashwini H

UTB27 - Part 2: ASIC Back-end Implementation of Chip-Level MIPS Processor cover

UTB27 - Part 2: ASIC Back-end Implementation of Chip-Level MIPS Processor

Dr Mamidi Nagaraju

UTB27 - Part-1: Front-end ASIC Design and Development of MIPS (RTL - LEC) cover

UTB27 - Part-1: Front-end ASIC Design and Development of MIPS (RTL - LEC)

Dr Mamidi Nagaraju, Ashwini H

UTB25 Design and Implementation of Elevator Controller using Cadence EDA Tools cover

UTB25 Design and Implementation of Elevator Controller using Cadence EDA Tools

Dr Mamidi Nagaraju, Ashwini H

UTB23 - Design and Implementation of 8-bit Magnitude Comparator using Cadence EDA tools (RTL - GDSII) cover

UTB23 - Design and Implementation of 8-bit Magnitude Comparator using Cadence EDA tools (RTL - GDSII)

Dr Mamidi Nagaraju, Ashwini H

UTB20 - ASIC Design and Implementation of Booth Multiplier using Cadence EDA tools (RTL - GDSII) cover

UTB20 - ASIC Design and Implementation of Booth Multiplier using Cadence EDA tools (RTL - GDSII)

Dr Mamidi Nagaraju